| contributor author | Q. Yao | |
| contributor author | J. Qu | |
| date accessioned | 2017-05-08T23:59:21Z | |
| date available | 2017-05-08T23:59:21Z | |
| date copyright | September, 1999 | |
| date issued | 1999 | |
| identifier issn | 1528-9044 | |
| identifier other | JEPAE4-26174#196_1.pdf | |
| identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/122002 | |
| description abstract | In this study, both two-dimensional and three-dimensional finite element analyses were used to study the stress distribution in and deflection of the flip chip assembly under thermal loading. It is found that the three-dimensional results compared favorably with experimental measurements, while the two-dimensional results consistently overestimate both stresses and deflection. Among the two-dimensional models, the plane stress assumption seems to yield results closer to the full three-dimensional predictions. Furthermore, three-dimensional models were used to investigate the effect of printed wiring board size on the overall deflection of the flip-chip assembly. This size effect of the printed wiring board has significant implications on the design of multi-chip modules. The results indicate that a square array placement pattern is preferable to a staggered array for multiple chip modules in order to reduce mechanical interaction between chips. For square arrays, such mechanical interaction between chips can be neglected when the minimum distance between adjacent chips is more than 2 times the chip size. | |
| publisher | The American Society of Mechanical Engineers (ASME) | |
| title | Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-Chip Packages | |
| type | Journal Paper | |
| journal volume | 121 | |
| journal issue | 3 | |
| journal title | Journal of Electronic Packaging | |
| identifier doi | 10.1115/1.2792684 | |
| journal fristpage | 196 | |
| journal lastpage | 201 | |
| identifier eissn | 1043-7398 | |
| keywords | Finite element analysis | |
| keywords | Modeling | |
| keywords | Flip-chip packages | |
| keywords | Deflection | |
| keywords | Stress | |
| keywords | Printed circuit boards | |
| keywords | Flip-chip assemblies | |
| keywords | Stress concentration | |
| keywords | Design | |
| keywords | Size effect | |
| keywords | Three-dimensional models | |
| keywords | Multi-chip modules AND Measurement | |
| tree | Journal of Electronic Packaging:;1999:;volume( 121 ):;issue: 003 | |
| contenttype | Fulltext | |