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contributor authorQ. Yao
contributor authorJ. Qu
date accessioned2017-05-08T23:59:21Z
date available2017-05-08T23:59:21Z
date copyrightSeptember, 1999
date issued1999
identifier issn1528-9044
identifier otherJEPAE4-26174#196_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/122002
description abstractIn this study, both two-dimensional and three-dimensional finite element analyses were used to study the stress distribution in and deflection of the flip chip assembly under thermal loading. It is found that the three-dimensional results compared favorably with experimental measurements, while the two-dimensional results consistently overestimate both stresses and deflection. Among the two-dimensional models, the plane stress assumption seems to yield results closer to the full three-dimensional predictions. Furthermore, three-dimensional models were used to investigate the effect of printed wiring board size on the overall deflection of the flip-chip assembly. This size effect of the printed wiring board has significant implications on the design of multi-chip modules. The results indicate that a square array placement pattern is preferable to a staggered array for multiple chip modules in order to reduce mechanical interaction between chips. For square arrays, such mechanical interaction between chips can be neglected when the minimum distance between adjacent chips is more than 2 times the chip size.
publisherThe American Society of Mechanical Engineers (ASME)
titleThree-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-Chip Packages
typeJournal Paper
journal volume121
journal issue3
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.2792684
journal fristpage196
journal lastpage201
identifier eissn1043-7398
keywordsFinite element analysis
keywordsModeling
keywordsFlip-chip packages
keywordsDeflection
keywordsStress
keywordsPrinted circuit boards
keywordsFlip-chip assemblies
keywordsStress concentration
keywordsDesign
keywordsSize effect
keywordsThree-dimensional models
keywordsMulti-chip modules AND Measurement
treeJournal of Electronic Packaging:;1999:;volume( 121 ):;issue: 003
contenttypeFulltext


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