Interfacial Thermal Stresses in Layered Structures: The Stepped Edge ProblemSource: Journal of Electronic Packaging:;1995:;volume( 117 ):;issue: 002::page 153Author:Wan-Lee Yin
DOI: 10.1115/1.2792083Publisher: The American Society of Mechanical Engineers (ASME)
Abstract: The intense, localized stress field produced by a temperature load in a multilayered structure may be significantly affected by the local geometry of the free edge. We examine here the stepped edge problem associated with bonding an elastic layer (silicon chip) to a single or multilayer substrate with a slightly larger length. Stress functions are introduced in various rectangular regions and the continuity of tractions are enforced across all inter-region boundaries. Furthermore, continuity of displacements is enforced across the junction of the two segments of the base laminate. The analysis results indicate that even a minute protrusion of the edge of the base laminate relative to the attached chip may cause significant changes in the peeling and shearing stresses in the end region of the interface.
keyword(s): Temperature , Laminates , Bonding , Stress , Silicon chips , Thermal stresses , Functions , Geometry , Junctions AND Shearing ,
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| contributor author | Wan-Lee Yin | |
| date accessioned | 2017-05-08T23:46:55Z | |
| date available | 2017-05-08T23:46:55Z | |
| date copyright | June, 1995 | |
| date issued | 1995 | |
| identifier issn | 1528-9044 | |
| identifier other | JEPAE4-26149#153_1.pdf | |
| identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/115164 | |
| description abstract | The intense, localized stress field produced by a temperature load in a multilayered structure may be significantly affected by the local geometry of the free edge. We examine here the stepped edge problem associated with bonding an elastic layer (silicon chip) to a single or multilayer substrate with a slightly larger length. Stress functions are introduced in various rectangular regions and the continuity of tractions are enforced across all inter-region boundaries. Furthermore, continuity of displacements is enforced across the junction of the two segments of the base laminate. The analysis results indicate that even a minute protrusion of the edge of the base laminate relative to the attached chip may cause significant changes in the peeling and shearing stresses in the end region of the interface. | |
| publisher | The American Society of Mechanical Engineers (ASME) | |
| title | Interfacial Thermal Stresses in Layered Structures: The Stepped Edge Problem | |
| type | Journal Paper | |
| journal volume | 117 | |
| journal issue | 2 | |
| journal title | Journal of Electronic Packaging | |
| identifier doi | 10.1115/1.2792083 | |
| journal fristpage | 153 | |
| journal lastpage | 158 | |
| identifier eissn | 1043-7398 | |
| keywords | Temperature | |
| keywords | Laminates | |
| keywords | Bonding | |
| keywords | Stress | |
| keywords | Silicon chips | |
| keywords | Thermal stresses | |
| keywords | Functions | |
| keywords | Geometry | |
| keywords | Junctions AND Shearing | |
| tree | Journal of Electronic Packaging:;1995:;volume( 117 ):;issue: 002 | |
| contenttype | Fulltext |