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contributor authorWan-Lee Yin
date accessioned2017-05-08T23:46:55Z
date available2017-05-08T23:46:55Z
date copyrightJune, 1995
date issued1995
identifier issn1528-9044
identifier otherJEPAE4-26149#153_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/115164
description abstractThe intense, localized stress field produced by a temperature load in a multilayered structure may be significantly affected by the local geometry of the free edge. We examine here the stepped edge problem associated with bonding an elastic layer (silicon chip) to a single or multilayer substrate with a slightly larger length. Stress functions are introduced in various rectangular regions and the continuity of tractions are enforced across all inter-region boundaries. Furthermore, continuity of displacements is enforced across the junction of the two segments of the base laminate. The analysis results indicate that even a minute protrusion of the edge of the base laminate relative to the attached chip may cause significant changes in the peeling and shearing stresses in the end region of the interface.
publisherThe American Society of Mechanical Engineers (ASME)
titleInterfacial Thermal Stresses in Layered Structures: The Stepped Edge Problem
typeJournal Paper
journal volume117
journal issue2
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.2792083
journal fristpage153
journal lastpage158
identifier eissn1043-7398
keywordsTemperature
keywordsLaminates
keywordsBonding
keywordsStress
keywordsSilicon chips
keywordsThermal stresses
keywordsFunctions
keywordsGeometry
keywordsJunctions AND Shearing
treeJournal of Electronic Packaging:;1995:;volume( 117 ):;issue: 002
contenttypeFulltext


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