Flow Characterization of Capillary Underfill in Multi-Chip Heterogenous Integration Using Computational Fluid Dynamics

Abstract

Underfill encapsulation is crucial in assembling flip-chip products, such as ball grid array packages, enhancing the reliability and performance of electronic packages by filling voids between integrated circuit chips and substrates. Despite advancements, challenges remain in understanding underfill flow dynamics in multichip heterogeneous systems. This study explores capillary underfill encapsulation in quad-chip configurations, integrating experimental observations with computational fluid dynamics (CFD) simulations to analyze underfill flow dynamics and their impact on package reliability. The CFD model shows high accuracy, with validation errors as low as 5.31% at a normalized time (tnz) of 0.02, 6.83% at 0.1, and 6.05% at 0.2. Among dispensing patterns, the Double-I pattern is most effective, minimizing void formation with percentages as low as 0.02%, compared to up to 1.96% and 2.39% for L and U patterns, respectively. The study also identifies an optimal dispensing length of 50% of the total chip length, reducing void percentages to 0.04%, compared to 9.32% and 12.84% at 100% and 30% lengths, respectively. These findings are pivotal for optimizing underfill processes, enhancing electronic package reliability and performance. The insights gained are crucial for advancing the design and manufacturing of state-of-the-art electronic devices, particularly in complex, heterogeneous integrations. This work provides a robust framework for improving the efficiency and reliability of electronic packaging solutions, paving the way for more durable and high-performance electronic devices.