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    Process-Factor Optimization of Small-Area Sintered Interconnects for Power Electronics Applications

    Source: Journal of Electronic Packaging:;2023:;volume( 145 ):;issue: 003::page 31008-1
    Author:
    Alzoubi, Khalid
    ,
    Hensel, Alexander
    ,
    Häußler, Felix
    ,
    Ottinger, Bettina
    ,
    Sippel, Marcel
    ,
    Franke, Jörg
    DOI: 10.1115/1.4056992
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: Power electronics is concerned with the use of electronic devices to control and transfer electric power from one form to another. Power electronics can be found in laptop chargers, electric grids, and solar inverters. Die-attach interconnections form a critical part of power electronics devices. Silver sintering has been traditionally used for die-attach interconnections because of its high melting point and ability to form very thin thicknesses. However, the processing time compared with soldering is very long. Sintered layers might contain large voids that affect the mechanical stability of the structure. Stresses caused by mechanical and environmental conditions might cause degradation and possibly early failures. This work focuses on studying the combined effect of process factors on the shear strength of small-area die-attach interconnections in silver sintering. Design of experiments (DoE) tools were used to build an experimental matrix with a 95% confidence level. The results have shown that holding time has a considerable effect on the mechanical stability of the die-attach interconnections. Intermetallic compounds formed in the sintered joints at higher holding times resulted in fewer voids. Furthermore, the treatment level of the holding time highly affects the shear strength under other factors such as temperature and pressure.
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      Process-Factor Optimization of Small-Area Sintered Interconnects for Power Electronics Applications

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    http://yetl.yabesh.ir/yetl1/handle/yetl/4291714
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    contributor authorAlzoubi, Khalid
    contributor authorHensel, Alexander
    contributor authorHäußler, Felix
    contributor authorOttinger, Bettina
    contributor authorSippel, Marcel
    contributor authorFranke, Jörg
    date accessioned2023-08-16T18:15:17Z
    date available2023-08-16T18:15:17Z
    date copyright3/8/2023 12:00:00 AM
    date issued2023
    identifier issn1043-7398
    identifier otherep_145_03_031008.pdf
    identifier urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4291714
    description abstractPower electronics is concerned with the use of electronic devices to control and transfer electric power from one form to another. Power electronics can be found in laptop chargers, electric grids, and solar inverters. Die-attach interconnections form a critical part of power electronics devices. Silver sintering has been traditionally used for die-attach interconnections because of its high melting point and ability to form very thin thicknesses. However, the processing time compared with soldering is very long. Sintered layers might contain large voids that affect the mechanical stability of the structure. Stresses caused by mechanical and environmental conditions might cause degradation and possibly early failures. This work focuses on studying the combined effect of process factors on the shear strength of small-area die-attach interconnections in silver sintering. Design of experiments (DoE) tools were used to build an experimental matrix with a 95% confidence level. The results have shown that holding time has a considerable effect on the mechanical stability of the die-attach interconnections. Intermetallic compounds formed in the sintered joints at higher holding times resulted in fewer voids. Furthermore, the treatment level of the holding time highly affects the shear strength under other factors such as temperature and pressure.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleProcess-Factor Optimization of Small-Area Sintered Interconnects for Power Electronics Applications
    typeJournal Paper
    journal volume145
    journal issue3
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.4056992
    journal fristpage31008-1
    journal lastpage31008-7
    page7
    treeJournal of Electronic Packaging:;2023:;volume( 145 ):;issue: 003
    contenttypeFulltext
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