Structural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack RetentionSource: Journal of Electronic Packaging:;2019:;volume( 141 ):;issue: 001::page 10801Author:Geng, Phil
DOI: 10.1115/1.4042800Publisher: The American Society of Mechanical Engineers (ASME)
Abstract: For more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.
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contributor author | Geng, Phil | |
date accessioned | 2019-03-17T10:10:19Z | |
date available | 2019-03-17T10:10:19Z | |
date copyright | 2/25/2019 12:00:00 AM | |
date issued | 2019 | |
identifier issn | 1043-7398 | |
identifier other | ep_141_01_010801.pdf | |
identifier uri | http://yetl.yabesh.ir/yetl1/handle/yetl/4255965 | |
description abstract | For more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group. | |
publisher | The American Society of Mechanical Engineers (ASME) | |
title | Structural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack Retention | |
type | Journal Paper | |
journal volume | 141 | |
journal issue | 1 | |
journal title | Journal of Electronic Packaging | |
identifier doi | 10.1115/1.4042800 | |
journal fristpage | 10801 | |
journal lastpage | 010801-8 | |
tree | Journal of Electronic Packaging:;2019:;volume( 141 ):;issue: 001 | |
contenttype | Fulltext |