Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package InteractionSource: Journal of Electronic Packaging:;2017:;volume( 139 ):;issue: 002::page 20906Author:Sukharev, Valeriy
,
Choy, Jun-Ho
,
Kteyan, Armen
,
Hovsepyan, Henrik
,
Nakamoto, Mark
,
Zhao, Wei
,
Radojcic, Riko
,
Muehle, Uwe
,
Zschech, Ehrenfried
DOI: 10.1115/1.4036402Publisher: The American Society of Mechanical Engineers (ASME)
Abstract: Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.
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contributor author | Sukharev, Valeriy | |
contributor author | Choy, Jun-Ho | |
contributor author | Kteyan, Armen | |
contributor author | Hovsepyan, Henrik | |
contributor author | Nakamoto, Mark | |
contributor author | Zhao, Wei | |
contributor author | Radojcic, Riko | |
contributor author | Muehle, Uwe | |
contributor author | Zschech, Ehrenfried | |
date accessioned | 2017-11-25T07:21:03Z | |
date available | 2017-11-25T07:21:03Z | |
date copyright | 2017/12/6 | |
date issued | 2017 | |
identifier issn | 1043-7398 | |
identifier other | ep_139_02_020906.pdf | |
identifier uri | http://138.201.223.254:8080/yetl1/handle/yetl/4236852 | |
description abstract | Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements. | |
publisher | The American Society of Mechanical Engineers (ASME) | |
title | Carrier Mobility Shift in Advanced Silicon Nodes Due to Chip-Package Interaction | |
type | Journal Paper | |
journal volume | 139 | |
journal issue | 2 | |
journal title | Journal of Electronic Packaging | |
identifier doi | 10.1115/1.4036402 | |
journal fristpage | 20906 | |
journal lastpage | 020906-12 | |
tree | Journal of Electronic Packaging:;2017:;volume( 139 ):;issue: 002 | |
contenttype | Fulltext |