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    Review and Projections of Integrated Cooling Systems for Three Dimensional Integrated Circuits

    Source: Journal of Electronic Packaging:;2014:;volume( 136 ):;issue: 002::page 24001
    Author:
    Kandlikar, Satish G.
    DOI: 10.1115/1.4027175
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current singlephase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 خ¼m or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.
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      Review and Projections of Integrated Cooling Systems for Three Dimensional Integrated Circuits

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    contributor authorKandlikar, Satish G.
    date accessioned2017-05-09T01:06:48Z
    date available2017-05-09T01:06:48Z
    date issued2014
    identifier issn1528-9044
    identifier otherep_136_02_024001.pdf
    identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/154468
    description abstractIn an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current singlephase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 خ¼m or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleReview and Projections of Integrated Cooling Systems for Three Dimensional Integrated Circuits
    typeJournal Paper
    journal volume136
    journal issue2
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.4027175
    journal fristpage24001
    journal lastpage24001
    identifier eissn1043-7398
    treeJournal of Electronic Packaging:;2014:;volume( 136 ):;issue: 002
    contenttypeFulltext
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    DSpace software copyright © 2002-2015  DuraSpace
    نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
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