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    On Failure Mechanisms in Flip Chip Assembly—Part 2: Optimal Underfill and Interconnecting Materials

    Source: Journal of Electronic Packaging:;2008:;volume( 130 ):;issue: 002::page 21009
    Author:
    Yoonchan Oh
    ,
    C. Steve Suh
    ,
    Hung-Jue Sue
    DOI: 10.1115/1.2912209
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: The physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and long-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield.
    keyword(s): Density , Solders , Fillers (Materials) , Epoxy adhesives , Waves , Failure mechanisms , Solder joints , Flip-chip , Flip-chip assemblies , Viscoelasticity , Reliability , Fatigue , Failure , Packaging , Materials properties , Wave propagation AND Clocks ,
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      On Failure Mechanisms in Flip Chip Assembly—Part 2: Optimal Underfill and Interconnecting Materials

    URI
    http://yetl.yabesh.ir/yetl1/handle/yetl/137773
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    contributor authorYoonchan Oh
    contributor authorC. Steve Suh
    contributor authorHung-Jue Sue
    date accessioned2017-05-09T00:27:36Z
    date available2017-05-09T00:27:36Z
    date copyrightJune, 2008
    date issued2008
    identifier issn1528-9044
    identifier otherJEPAE4-26285#021009_1.pdf
    identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/137773
    description abstractThe physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and long-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleOn Failure Mechanisms in Flip Chip Assembly—Part 2: Optimal Underfill and Interconnecting Materials
    typeJournal Paper
    journal volume130
    journal issue2
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.2912209
    journal fristpage21009
    identifier eissn1043-7398
    keywordsDensity
    keywordsSolders
    keywordsFillers (Materials)
    keywordsEpoxy adhesives
    keywordsWaves
    keywordsFailure mechanisms
    keywordsSolder joints
    keywordsFlip-chip
    keywordsFlip-chip assemblies
    keywordsViscoelasticity
    keywordsReliability
    keywordsFatigue
    keywordsFailure
    keywordsPackaging
    keywordsMaterials properties
    keywordsWave propagation AND Clocks
    treeJournal of Electronic Packaging:;2008:;volume( 130 ):;issue: 002
    contenttypeFulltext
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    DSpace software copyright © 2002-2015  DuraSpace
    نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
    yabeshDSpacePersian