contributor author | Tong Hong Wang | |
contributor author | Chang-Chi Lee | |
contributor author | Yi-Shao Lai | |
contributor author | Yu-Cheng Lin | |
date accessioned | 2017-05-09T00:19:35Z | |
date available | 2017-05-09T00:19:35Z | |
date copyright | September, 2006 | |
date issued | 2006 | |
identifier issn | 1528-9044 | |
identifier other | JEPAE4-26264#281_1.pdf | |
identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/133531 | |
description abstract | In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling. | |
publisher | The American Society of Mechanical Engineers (ASME) | |
title | Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions | |
type | Journal Paper | |
journal volume | 128 | |
journal issue | 3 | |
journal title | Journal of Electronic Packaging | |
identifier doi | 10.1115/1.2229229 | |
journal fristpage | 281 | |
journal lastpage | 284 | |
identifier eissn | 1043-7398 | |
keywords | Temperature | |
keywords | Vehicles | |
keywords | Boundary-value problems | |
keywords | Thermal analysis AND Junctions | |
tree | Journal of Electronic Packaging:;2006:;volume( 128 ):;issue: 003 | |
contenttype | Fulltext | |