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    Test Methods for Silicon Die Strength

    Source: Journal of Electronic Packaging:;2006:;volume( 128 ):;issue: 004::page 419
    Author:
    M. Y. Tsai
    ,
    C. H. Chen
    ,
    C. S. Lin
    DOI: 10.1115/1.2351907
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: Recently, the 3D or stacked-die packages become increasingly popular for packaging ICs into a system or subsystem to satisfy the needs of low cost, small form factor, and high performance. For the applications of these packages, IC silicon wafers have to be ground to be relatively thin through the wafer-thinning processes (such as grinding, polishing, and plasma etching). The strength of dies has to be determined for the design requirement and reliability assurance of the packages. From the published data, there still exist some issues, including a large scatter existed in die strength data and difficulties in differentiating the causes of the low strength between from the wafer grinding and from wafer sawing by either the three-point bending or four-point bending test. The purposes of this study are to develop new, reliable, and simple test methods for determination of die strength, in order to improve the data scatter, and to provide a solution for differentiating the factors that affect the variability of die strength for finding out the causes of the weakness of the die strength. In this study, two new test methods, point-loaded circular plate with simple supports test (PLT-I) and point-loaded plate on elastic foundation test (PLT-II), are proposed and then evaluated by testing two groups of silicon dies with different surface conditions. The surface conditions (roughness) of the specimens are determined by atomic force microscopy and correlated to failure strength. The failure forces from both tests have to be modified by using maximum stress obtained from theories or finite element analyses to obtain the failure strength. The test results are compared to each other and further with a widely used four-point bending test. The results suggest that, unlike the four-point bending test suffering the chipping effect, both methods provide very consistent data with a small scatter for each group of specimens and can be used for identifying the effect of surface grinding (roughness) on the die strength. It is also shown that the die strength is highly dependent on the surface roughness. Accordingly, these two methods can provide not only a (biaxial) stress field similar to temperature-loaded die in the packages, but also simple, feasible, reliable, and chipping-free tests for silicon dies of dummy or real IC chips, without strict geometrical limitation, such as beam-type geometry for the three-point or four-point bending test.
    keyword(s): Force , Stress , Silicon , Failure , Finite element analysis , Deflection AND Semiconductor wafers ,
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      Test Methods for Silicon Die Strength

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    contributor authorM. Y. Tsai
    contributor authorC. H. Chen
    contributor authorC. S. Lin
    date accessioned2017-05-09T00:19:32Z
    date available2017-05-09T00:19:32Z
    date copyrightDecember, 2006
    date issued2006
    identifier issn1528-9044
    identifier otherJEPAE4-26266#419_1.pdf
    identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/133507
    description abstractRecently, the 3D or stacked-die packages become increasingly popular for packaging ICs into a system or subsystem to satisfy the needs of low cost, small form factor, and high performance. For the applications of these packages, IC silicon wafers have to be ground to be relatively thin through the wafer-thinning processes (such as grinding, polishing, and plasma etching). The strength of dies has to be determined for the design requirement and reliability assurance of the packages. From the published data, there still exist some issues, including a large scatter existed in die strength data and difficulties in differentiating the causes of the low strength between from the wafer grinding and from wafer sawing by either the three-point bending or four-point bending test. The purposes of this study are to develop new, reliable, and simple test methods for determination of die strength, in order to improve the data scatter, and to provide a solution for differentiating the factors that affect the variability of die strength for finding out the causes of the weakness of the die strength. In this study, two new test methods, point-loaded circular plate with simple supports test (PLT-I) and point-loaded plate on elastic foundation test (PLT-II), are proposed and then evaluated by testing two groups of silicon dies with different surface conditions. The surface conditions (roughness) of the specimens are determined by atomic force microscopy and correlated to failure strength. The failure forces from both tests have to be modified by using maximum stress obtained from theories or finite element analyses to obtain the failure strength. The test results are compared to each other and further with a widely used four-point bending test. The results suggest that, unlike the four-point bending test suffering the chipping effect, both methods provide very consistent data with a small scatter for each group of specimens and can be used for identifying the effect of surface grinding (roughness) on the die strength. It is also shown that the die strength is highly dependent on the surface roughness. Accordingly, these two methods can provide not only a (biaxial) stress field similar to temperature-loaded die in the packages, but also simple, feasible, reliable, and chipping-free tests for silicon dies of dummy or real IC chips, without strict geometrical limitation, such as beam-type geometry for the three-point or four-point bending test.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleTest Methods for Silicon Die Strength
    typeJournal Paper
    journal volume128
    journal issue4
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.2351907
    journal fristpage419
    journal lastpage426
    identifier eissn1043-7398
    keywordsForce
    keywordsStress
    keywordsSilicon
    keywordsFailure
    keywordsFinite element analysis
    keywordsDeflection AND Semiconductor wafers
    treeJournal of Electronic Packaging:;2006:;volume( 128 ):;issue: 004
    contenttypeFulltext
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