Development of Novel Filler Technology for No-Flow and Wafer Level Underfill MaterialsSource: Journal of Electronic Packaging:;2005:;volume( 127 ):;issue: 002::page 77Author:Slawomir Rubinsztajn
,
Donald Buckley
,
John Campbell
,
David Esler
,
Eric Fiveland
,
Ananth Prabhakumar
,
Donna Sherman
,
Sandeep Tonapi
DOI: 10.1115/1.1846067Publisher: The American Society of Mechanical Engineers (ASME)
Abstract: Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.
keyword(s): Flow (Dynamics) , Fillers (Materials) , Semiconductor wafers , Resins , Flip-chip , Solder joints , Reliability , Solders , Curing , Silicon AND Thermal expansion ,
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contributor author | Slawomir Rubinsztajn | |
contributor author | Donald Buckley | |
contributor author | John Campbell | |
contributor author | David Esler | |
contributor author | Eric Fiveland | |
contributor author | Ananth Prabhakumar | |
contributor author | Donna Sherman | |
contributor author | Sandeep Tonapi | |
date accessioned | 2017-05-09T00:15:52Z | |
date available | 2017-05-09T00:15:52Z | |
date copyright | June, 2005 | |
date issued | 2005 | |
identifier issn | 1528-9044 | |
identifier other | JEPAE4-26243#77_1.pdf | |
identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/131643 | |
description abstract | Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation. | |
publisher | The American Society of Mechanical Engineers (ASME) | |
title | Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials | |
type | Journal Paper | |
journal volume | 127 | |
journal issue | 2 | |
journal title | Journal of Electronic Packaging | |
identifier doi | 10.1115/1.1846067 | |
journal fristpage | 77 | |
journal lastpage | 85 | |
identifier eissn | 1043-7398 | |
keywords | Flow (Dynamics) | |
keywords | Fillers (Materials) | |
keywords | Semiconductor wafers | |
keywords | Resins | |
keywords | Flip-chip | |
keywords | Solder joints | |
keywords | Reliability | |
keywords | Solders | |
keywords | Curing | |
keywords | Silicon AND Thermal expansion | |
tree | Journal of Electronic Packaging:;2005:;volume( 127 ):;issue: 002 | |
contenttype | Fulltext |