Warpage Analysis of Underfilled Wafers

Abstract

Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes. After wafer dicing, warpage could affect the quality of the dies and shorten the life of each packaged product. Many documented works indicated that in the design and implementation of multilayer structured electronic packaging products, some key parameters must be carefully considered and closely controlled to ensure the best packaging quality with the minimum warpage. During the wafer-level flip chip assembly process, the application of underfill on the whole wafer is a critical step. In this step, the key underfill parameters that affect wafer warpage are Young’s modulus, thickness, and coefficient of thermal expansion (CTE). In this paper, an experimental design and statistical methods were used to identify the model structure and parameters that are critical to the warpage of wafers. Bilinear regression models were identified based on the data obtained from finite element analysis (FEA) that was verified by shadow moiré experiments. In FEA, the underfilled wafer structure is simplified to consisting of two layers of linear elastic materials. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE primarily determine wafer warpage. Further FEA and shadow moiré experiments indicate that the models are capable of predicting wafer warpage in the WLP processes.