| contributor author | Jerry Su | |
| contributor author | Francis Su | |
| contributor author | Shou-Kang Chen | |
| contributor author | Sheng-Jye Hwang | |
| date accessioned | 2017-05-09T00:09:57Z | |
| date available | 2017-05-09T00:09:57Z | |
| date copyright | March, 2003 | |
| date issued | 2003 | |
| identifier issn | 1528-9044 | |
| identifier other | JEPAE4-26212#139_1.pdf | |
| identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/128254 | |
| description abstract | Various methodologies of wire sweep analysis have been introduced to get better prediction and matching the experimental measurements by many researchers. As more and more high pin-count packages (such as BGA, QFP) are used today, efficiency has become an important requirement besides accuracy for software used to predict wire sweep in IC packaging. This study introduces a newly developed wire sweep analysis solution (InPack), not only to meet the need of accuracy, but also enhance the efficiency for actual applications. It combines global flow analysis (C-MOLD) and structure analysis (ANSYS) to become a solution for general wire sweep analysis. | |
| publisher | The American Society of Mechanical Engineers (ASME) | |
| title | An Efficient Solution for Wire Sweep Analysis in IC Packaging | |
| type | Journal Paper | |
| journal volume | 125 | |
| journal issue | 1 | |
| journal title | Journal of Electronic Packaging | |
| identifier doi | 10.1115/1.1535447 | |
| journal fristpage | 139 | |
| journal lastpage | 143 | |
| identifier eissn | 1043-7398 | |
| keywords | Wire | |
| keywords | Integrated circuit packaging | |
| keywords | Integrated circuits AND Flow (Dynamics) | |
| tree | Journal of Electronic Packaging:;2003:;volume( 125 ):;issue: 001 | |
| contenttype | Fulltext | |
