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contributor authorK. Darbha
contributor authorJ. H. Okura
contributor authorA. Dasgupta
date accessioned2017-05-08T23:59:19Z
date available2017-05-08T23:59:19Z
date copyrightDecember, 1999
date issued1999
identifier issn1528-9044
identifier otherJEPAE4-26175#231_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/121977
description abstractA generalized multi-domain Rayleigh-Ritz (MDRR) approach developed by Ling and Dasgupta (1995), is extended in this paper, to obtain the stress field in flip chip solder interconnects, under cyclic thermal loading. Elastic, Plastic and time-dependent visco-plastic analysis is demonstrated on flip chip solder interconnects. The method has been applied to other surface-mount interconnects in the past such as J-lead (Ling and Dasgupta, 1996a) and ball-grid joints (Ling and Dasgupta, 1997). The analysis results for the J-lead and ball grid joints have confirmed that the MDRR technique is capable of providing stress-strain hysteresis with adequate accuracy, at a fraction of the modeling effort required for finite element model generation and analyses. Nonlinear viscoplastic stress analysis results for flip chip interconnects without underfill are presented in this paper. The fatigue endurance of the solder joints is assessed by combining results from this stress analysis model with an energy-partitioning damage model (Dasgupta et al., 1992). The life predicted by the analytical damage model is compared with experimental results.
publisherThe American Society of Mechanical Engineers (ASME)
titleThermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 1—Without Underfill
typeJournal Paper
journal volume121
journal issue4
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.2793845
journal fristpage231
journal lastpage236
identifier eissn1043-7398
keywordsDurability
keywordsSolders
keywordsFlip-chip
keywordsStress
keywordsStress analysis (Engineering)
keywordsFatigue
keywordsModeling
keywordsFinite element model
keywordsSolder joints AND Surface mount packaging
treeJournal of Electronic Packaging:;1999:;volume( 121 ):;issue: 004
contenttypeFulltext


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