Analysis of Bending and Shearing of Tri-Layer Laminations for Solder Joint ReliabilitySource: Journal of Electronic Packaging:;1998:;volume( 120 ):;issue: 003::page 221Author:E. K. Buratynski
DOI: 10.1115/1.2792626Publisher: The American Society of Mechanical Engineers (ASME)
Abstract: For solder joint reliability reasons, direct chip attach technology uses an underfill material to restrict the movement of the silicon die relative to the substrate due to differences in their coefficients of thermal expansion. Modeling the fatigue life of a solder joint assembled with this technology requires a shear strain versus applied shear stress relationship. The direct chip attach configuration can be modeled as a tri-layer lamination that bends and shears with temperature excursions from the stress-free temperature. The present analysis formulates an axisymmetric, tri-layer, elastic material stress model with finite radii for the silicon die and underfill layer and an infinite sized substrate layer. A closed form solution to the shear distributions at the interfaces and the bending of the lamination is presented. This solution is a function of the reactant forces exerted by solder joints and forms the basis of a fatigue life model.
keyword(s): Reliability , Laminations , Shearing , Solder joints , Stress , Shear (Mechanics) , Temperature , Fatigue life , Silicon , Force , Thermal expansion AND Modeling ,
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contributor author | E. K. Buratynski | |
date accessioned | 2017-05-08T23:56:14Z | |
date available | 2017-05-08T23:56:14Z | |
date copyright | September, 1998 | |
date issued | 1998 | |
identifier issn | 1528-9044 | |
identifier other | JEPAE4-26167#221_1.pdf | |
identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/120242 | |
description abstract | For solder joint reliability reasons, direct chip attach technology uses an underfill material to restrict the movement of the silicon die relative to the substrate due to differences in their coefficients of thermal expansion. Modeling the fatigue life of a solder joint assembled with this technology requires a shear strain versus applied shear stress relationship. The direct chip attach configuration can be modeled as a tri-layer lamination that bends and shears with temperature excursions from the stress-free temperature. The present analysis formulates an axisymmetric, tri-layer, elastic material stress model with finite radii for the silicon die and underfill layer and an infinite sized substrate layer. A closed form solution to the shear distributions at the interfaces and the bending of the lamination is presented. This solution is a function of the reactant forces exerted by solder joints and forms the basis of a fatigue life model. | |
publisher | The American Society of Mechanical Engineers (ASME) | |
title | Analysis of Bending and Shearing of Tri-Layer Laminations for Solder Joint Reliability | |
type | Journal Paper | |
journal volume | 120 | |
journal issue | 3 | |
journal title | Journal of Electronic Packaging | |
identifier doi | 10.1115/1.2792626 | |
journal fristpage | 221 | |
journal lastpage | 228 | |
identifier eissn | 1043-7398 | |
keywords | Reliability | |
keywords | Laminations | |
keywords | Shearing | |
keywords | Solder joints | |
keywords | Stress | |
keywords | Shear (Mechanics) | |
keywords | Temperature | |
keywords | Fatigue life | |
keywords | Silicon | |
keywords | Force | |
keywords | Thermal expansion AND Modeling | |
tree | Journal of Electronic Packaging:;1998:;volume( 120 ):;issue: 003 | |
contenttype | Fulltext |