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    Approximating the Steiner Tree in the Placement Process

    Source: Journal of Electronic Packaging:;1989:;volume( 111 ):;issue: 003::page 228
    Author:
    Yeun Tsun Wong
    ,
    Michael Pecht
    DOI: 10.1115/1.3226538
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: By simulating the movement of a node in a tree, an iso-distance error graph (IDEG) which contains connection errors generated by replacing a Steiner tree with its equivalent non-Steiner tree is developed. The IDEG is used to estimate how well various types of non-Steiner trees function as a Steiner tree in the placement of components on a printed wiring board (PWB). To reduce connection errors in the IDEG and pursue computational efficiency, a row-based tree family in which the tree length is primarily dependent on the terminal coordinates of each row, is constructed. Then, based on the analysis of the error distribution on the IDEG, the row-based trees and the spanning tree are compared in terms of their approximation to the Steiner tree.
    keyword(s): Tree (Data structure) , Errors , Printed circuit boards AND Approximation ,
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      Approximating the Steiner Tree in the Placement Process

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    http://yetl.yabesh.ir/yetl1/handle/yetl/105247
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    contributor authorYeun Tsun Wong
    contributor authorMichael Pecht
    date accessioned2017-05-08T23:29:44Z
    date available2017-05-08T23:29:44Z
    date copyrightSeptember, 1989
    date issued1989
    identifier issn1528-9044
    identifier otherJEPAE4-26110#228_1.pdf
    identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/105247
    description abstractBy simulating the movement of a node in a tree, an iso-distance error graph (IDEG) which contains connection errors generated by replacing a Steiner tree with its equivalent non-Steiner tree is developed. The IDEG is used to estimate how well various types of non-Steiner trees function as a Steiner tree in the placement of components on a printed wiring board (PWB). To reduce connection errors in the IDEG and pursue computational efficiency, a row-based tree family in which the tree length is primarily dependent on the terminal coordinates of each row, is constructed. Then, based on the analysis of the error distribution on the IDEG, the row-based trees and the spanning tree are compared in terms of their approximation to the Steiner tree.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleApproximating the Steiner Tree in the Placement Process
    typeJournal Paper
    journal volume111
    journal issue3
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.3226538
    journal fristpage228
    journal lastpage235
    identifier eissn1043-7398
    keywordsTree (Data structure)
    keywordsErrors
    keywordsPrinted circuit boards AND Approximation
    treeJournal of Electronic Packaging:;1989:;volume( 111 ):;issue: 003
    contenttypeFulltext
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    DSpace software copyright © 2002-2015  DuraSpace
    نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
    yabeshDSpacePersian