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contributor authorShah, Jimil M.
contributor authorCrandall, Thomas
contributor authorTuma, Phillip E.
date accessioned2023-11-29T18:33:36Z
date available2023-11-29T18:33:36Z
date copyright5/15/2023 12:00:00 AM
date issued5/15/2023 12:00:00 AM
date issued2023-05-15
identifier issn1043-7398
identifier otherep_145_04_041101.pdf
identifier urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4294222
description abstractTwo-phase immersion cooling (2PIC) has been proposed as a means of economically increasing overall energy efficiency while accommodating increased chip powers and system-level power density. Designers unfamiliar with Two-phase immersion technology may be unaware of the chip-level thermal performance capabilities of the technology. This performance, in the case of a lidded processor, is quantified as a case-to-fluid thermal resistance, Rcf. This work made use of boiler assemblies comprised of copper plates to which two porous metallic boiling enhancement coatings (BECs) had been applied. These boiler assemblies were applied with conventional thermal grease to a thermal test vehicle (TTV) emulating the Skylake series of 8th Gen Intel® Xeon® CPUs and a thermal test slug (TTS) emulating the Advanced Micro Devices, Inc. (AMD) EPYCTM processors. Both were tested in saturated 3MTM FluorinertTM FC-3284 fluid. The lowest Rcf = 0.020 °C/W was achieved on the TTS at 350 W. The paper also includes additional TTS data gathered with different boiler assemblies and Thermal Interface Materials as well as field data in the form of Rcf or junction-to-fluid thermal resistances, Rjf, for different live silicon chips.
publisherThe American Society of Mechanical Engineers (ASME)
titleChip Level Thermal Performance Measurements in Two-Phase Immersion Cooling
typeJournal Paper
journal volume145
journal issue4
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.4062403
journal fristpage41101-1
journal lastpage41101-7
page7
treeJournal of Electronic Packaging:;2023:;volume( 145 ):;issue: 004
contenttypeFulltext


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