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contributor authorLau, John H.
date accessioned2019-09-18T09:07:24Z
date available2019-09-18T09:07:24Z
date copyright5/17/2019 12:00:00 AM
date issued2019
identifier issn1043-7398
identifier otherep_141_04_040801
identifier urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4259123
description abstractThe recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.
publisherAmerican Society of Mechanical Engineers (ASME)
titleRecent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging
typeJournal Paper
journal volume141
journal issue4
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.4043341
journal fristpage40801
journal lastpage040801-27
treeJournal of Electronic Packaging:;2019:;volume( 141 ):;issue: 004
contenttypeFulltext


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