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contributor authorS. Han
contributor authorK. K. Wang
date accessioned2017-05-09T00:02:12Z
date available2017-05-09T00:02:12Z
date copyrightJune, 2000
date issued2000
identifier issn1528-9044
identifier otherJEPAE4-26181#160_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/123563
description abstractIn this paper, methods to analyze the flow during semiconductor chip encapsulation have been developed. A numerical method is used for the flow analysis in the chip cavity. In this study, for accurate analysis of flow in the chip cavity, models for the cross flow through the leadframe openings have been developed. The models have been verified by comparing with two experiments. In the first experiment, clear polymer and transparent mold have been used for the visualization of flow in a cavity with a leadframe. In the next experiment, actual epoxy molding compound together with an industrial encapsulation process have been used to observe the melt-front advancement shapes. The calculated and experimental results show good agreement. [S1043-7398(00)00902-6]
publisherThe American Society of Mechanical Engineers (ASME)
titleFlow Analysis in a Chip Cavity During Semiconductor Encapsulation
typeJournal Paper
journal volume122
journal issue2
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.483149
journal fristpage160
journal lastpage167
identifier eissn1043-7398
keywordsFlow (Dynamics)
keywordsCavities
keywordsIntegrated circuits
keywordsSemiconductors (Materials) AND Thickness
treeJournal of Electronic Packaging:;2000:;volume( 122 ):;issue: 002
contenttypeFulltext


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