| contributor author | C. Basaran | |
| contributor author | C. S. Desai | |
| contributor author | T. Kundu | |
| date accessioned | 2017-05-08T23:56:20Z | |
| date available | 2017-05-08T23:56:20Z | |
| date copyright | March, 1998 | |
| date issued | 1998 | |
| identifier issn | 1528-9044 | |
| identifier other | JEPAE4-26165#48_1.pdf | |
| identifier uri | http://yetl.yabesh.ir/yetl/handle/yetl/120287 | |
| description abstract | The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory. | |
| publisher | The American Society of Mechanical Engineers (ASME) | |
| title | Thermomechanical Finite Element Analysis of Problems in Electronic Packaging Using the Disturbed State Concept: Part 2—Verification and Application | |
| type | Journal Paper | |
| journal volume | 120 | |
| journal issue | 1 | |
| journal title | Journal of Electronic Packaging | |
| identifier doi | 10.1115/1.2792285 | |
| journal fristpage | 48 | |
| journal lastpage | 53 | |
| identifier eissn | 1043-7398 | |
| keywords | Electronic packaging | |
| keywords | Finite element analysis | |
| keywords | Alloys | |
| keywords | Solders | |
| keywords | Modeling AND Surface mount technology | |
| tree | Journal of Electronic Packaging:;1998:;volume( 120 ):;issue: 001 | |
| contenttype | Fulltext | |
