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contributor authorR. K. Sahoo
contributor authorJ. Talbott
contributor authorK. P. Gupta
contributor authorV. Prasad
contributor authorI. Kao
date accessioned2017-05-08T23:56:19Z
date available2017-05-08T23:56:19Z
date copyrightMarch, 1998
date issued1998
identifier issn1528-9044
identifier otherJEPAE4-26165#35_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/120285
description abstractCrystalline and polycrystalline ingots of silicon and other materials need to be cut into thin wafers for microelectronics, photovoltaics, and many other applications. For slicing process to be cost-effective, the kerf loss should be minimum and the surface finish should be of a high quality. Wire saw can meet these demands and is considered to be a potentially better technology than the inner diameter (ID) saw. An initial study of the current technology shows that the wire saw cutting is a poorly understood process, and no model exists for simulation, design, and control of this process. The wire saw slicing process can be well modeled as a cutting process, where the initial fracture occurs because of the stress distribution between the two surfaces subjected to compressive loading and sliding friction. A preliminary analysis is carried out using a standard finite element method to develop a better understanding of this process and to determine possible ways of improving the process design. The results of vibration (modal) and thermal stress analyses show that an accurate prediction of the effects of process parameters would help in improving the wire saw design. Similarly, a proper feedback control algorithm would enable a better control of the process by using on-line information on wire tension and stiffness, temperature, and other relevant quantities. A methodology for systematic approach to analysis and design of an advanced wire saw process is also outlined.
publisherThe American Society of Mechanical Engineers (ASME)
titleTowards an Integrated Approach for Analysis and Design of Wafer Slicing by a Wire Saw
typeJournal Paper
journal volume120
journal issue1
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.2792283
journal fristpage35
journal lastpage40
identifier eissn1043-7398
keywordsWire
keywordsSemiconductor wafers
keywordsSurface acoustic waves
keywordsDesign
keywordsCutting
keywordsFeedback
keywordsProcess design
keywordsSilicon
keywordsSliding friction
keywordsStiffness
keywordsTension
keywordsMicroelectronic devices
keywordsThermal stresses
keywordsFinite element methods
keywordsStress concentration
keywordsAlgorithms
keywordsSimulation
keywordsFinishes
keywordsFracture (Process)
keywordsPhotovoltaics
keywordsVibration AND Temperature
treeJournal of Electronic Packaging:;1998:;volume( 120 ):;issue: 001
contenttypeFulltext


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