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contributor authorBarabadi, Banafsheh
contributor authorKumar, Satish
contributor authorJoshi, Yogendra K.
date accessioned2017-11-25T07:16:53Z
date available2017-11-25T07:16:53Z
date copyright2017/21/3
date issued2017
identifier issn0022-1481
identifier otherht_139_07_072101.pdf
identifier urihttp://138.201.223.254:8080/yetl1/handle/yetl/4234270
description abstractA major challenge in maintaining quality and reliability in today's microelectronics chips comes from the ever increasing levels of integration in the device fabrication, as well as from the high current densities. Transient Joule heating in the on-chip interconnect metal lines with characteristic sizes of tens of nanometer, can lead to thermomechanical fatigue and failure due to the thermal expansion coefficient mismatch between different materials. Full-field simulations of nearly a billion interconnects in a modern microprocessor are infeasible due to the grid size requirements. To prevent premature device failures, a rapid predictive capability for the thermal response of on-chip interconnects is essential. This work develops a two-dimensional (2D) transient heat conduction framework to analyze inhomogeneous domains, using a reduced-order modeling approach based on proper orthogonal decomposition (POD) and Galerkin projection. POD modes are generated by using a representative step function as the heat source. The model rapidly predicted the transient thermal behavior of the system for several cases, without generating any new observations, and using just a few POD modes.
publisherThe American Society of Mechanical Engineers (ASME)
titleTransient Heat Conduction in On-Chip Interconnects Using Proper Orthogonal Decomposition Method
typeJournal Paper
journal volume139
journal issue7
journal titleJournal of Heat Transfer
identifier doi10.1115/1.4035889
journal fristpage72101
journal lastpage072101-10
treeJournal of Heat Transfer:;2017:;volume( 139 ):;issue: 007
contenttypeFulltext


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