Error Minimization in Layered Manufacturing Parts by Stereolithography File Modification Using a Vertex Translation Algorithm

Abstract

Layered manufacturing (LM) machines use stereolithography (STL) files to build parts by creating continuous slices on top of each other. An STL file approximates the surface of a part with planar triangles. This results in geometric errors being introduced in the part surface during the conversion from the CAD model to the STL file format, which in turn leads to errors in the LM manufactured part. CAD packages have builtin export options to reduce this CAD to STL conversion error. However, this is applied to the entire part geometry which leads to an increase in the file size and preprocessing time in LM machines. This paper presents a new approach to locally reduce this CAD to STL translation error. This approach, referred to as vertex translation algorithm (VTA), compares an STL facet to its corresponding CAD surface, computes the chordal error at multiple points on the STL surface, and translates the point with the maximum chordal error until it lies on the design surface. This translation results in the reduction of the chordal error locally without unnecessarily increasing the size of the STL file. In addition, a facet isolation algorithm (FIA) has also been developed and presented in this paper. This isolation algorithm extracts the STL facets corresponding to the surfaces and features of the part that have to be modified by the translation algorithm. The VTA is applied in conjunction with the FIA on a sample service part to reduce the form and profile error of critical features of the part in order to satisfy the tolerance callouts on the part.