| description abstract | The photovoltaic industry is experiencing rapid growth. Industry analysts project that photovoltaic sales will increase from their current $1.5 billion level to over $27 billion by 2020, representing an average growth rate of 25%. (Cook et. al. 2000)[1]. To date, the vast majority of sales have been for navigational signals, call boxes, telecommunication centers, consumer products, off-grid electrification projects, and small grid-interactive residential rooftop applications. Building integrated photovoltaics, the integration of photovoltaic cells into one or more of the exterior surfaces of the building envelope, represents a small but growing photovoltaic application. In order for building owners, designers, and architects to make informed economic decisions regarding the use of building integrated photovoltaics, accurate predictive tools and performance data are needed. A building integrated photovoltaic test bed has been constructed at the National Institute of Standards and Technology to provide the performance data needed for model validation. The facility incorporates four identical pairs of building integrated photovoltaic panels constructed using single-crystalline, polycrystalline, silicon film, and amorphous silicon photovoltaic cells. One panel of each identical pair is installed with thermal insulation attached to its rear surface. The second paired panel is installed without thermal insulation. This experimental configuration yields results that quantify the effect of elevated cell temperature on the panels’ performance for different cell technologies. This paper presents the first set of experimental results from this facility. Comparisons are made between the electrical performance of the insulated and non-insulated panels for each of the four cell technologies. The monthly and overall conversion efficiencies for each cell technology are presented and the seasonal performance variations discussed. Daily efficiencies are presented for a selected month. Finally, plots of the power output and panel temperatures are presented and discussed for the single-crystalline and amorphous silicon panels. | |
