YaBeSH Engineering and Technology Library

    • Journals
    • PaperQuest
    • YSE Standards
    • YaBeSH
    • Login
    View Item 
    •   YE&T Library
    • ASME
    • Journal of Electronic Packaging
    • View Item
    •   YE&T Library
    • ASME
    • Journal of Electronic Packaging
    • View Item
    • All Fields
    • Source Title
    • Year
    • Publisher
    • Title
    • Subject
    • Author
    • DOI
    • ISBN
    Advanced Search
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Archive

    Optimal Chip Layout on a Printed Circuit Board Using Design Sensitivity Analysis of Subdomain Configuration

    Source: Journal of Electronic Packaging:;1995:;volume( 117 ):;issue: 004::page 275
    Author:
    Seo Jin Joo
    ,
    Byung Man Kwak
    DOI: 10.1115/1.2792105
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: A chip layout problem is formulated as a new class of shape optimal design called a subdomain optimization, where the chips correspond to subdomains whose configuration and location are to be decided. Shape design sensitivity analysis for a perturbed subdomain is made based on the concept of material derivative and adjoint system. Introducing a suitable category of design velocity fields, the change of the configuration is adequately describable. Sensitivities and optimal positions of chips on a printed circuit board are obtained and their accuracy discussed.
    keyword(s): Design sensitivity analysis , Printed circuit boards , Design , Shapes AND Optimization ,
    • Download: (581.2Kb)
    • Show Full MetaData Hide Full MetaData
    • Get RIS
    • Item Order
    • Go To Publisher
    • Statistics

      Optimal Chip Layout on a Printed Circuit Board Using Design Sensitivity Analysis of Subdomain Configuration

    URI
    https://yetl.yabesh.ir/yetl1/handle/yetl/115126
    Collections
    • Journal of Electronic Packaging

    Show full item record

    contributor authorSeo Jin Joo
    contributor authorByung Man Kwak
    date accessioned2017-05-08T23:46:52Z
    date available2017-05-08T23:46:52Z
    date copyrightDecember, 1995
    date issued1995
    identifier issn1528-9044
    identifier otherJEPAE4-26151#275_1.pdf
    identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/115126
    description abstractA chip layout problem is formulated as a new class of shape optimal design called a subdomain optimization, where the chips correspond to subdomains whose configuration and location are to be decided. Shape design sensitivity analysis for a perturbed subdomain is made based on the concept of material derivative and adjoint system. Introducing a suitable category of design velocity fields, the change of the configuration is adequately describable. Sensitivities and optimal positions of chips on a printed circuit board are obtained and their accuracy discussed.
    publisherThe American Society of Mechanical Engineers (ASME)
    titleOptimal Chip Layout on a Printed Circuit Board Using Design Sensitivity Analysis of Subdomain Configuration
    typeJournal Paper
    journal volume117
    journal issue4
    journal titleJournal of Electronic Packaging
    identifier doi10.1115/1.2792105
    journal fristpage275
    journal lastpage280
    identifier eissn1043-7398
    keywordsDesign sensitivity analysis
    keywordsPrinted circuit boards
    keywordsDesign
    keywordsShapes AND Optimization
    treeJournal of Electronic Packaging:;1995:;volume( 117 ):;issue: 004
    contenttypeFulltext
    DSpace software copyright © 2002-2015  DuraSpace
    نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
    yabeshDSpacePersian
     
    DSpace software copyright © 2002-2015  DuraSpace
    نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
    yabeshDSpacePersian