| dc.contributor.author | Lau, John H. | |
| dc.date.accessioned | 2019-09-18T09:07:24Z | |
| dc.date.available | 2019-09-18T09:07:24Z | |
| dc.date.copyright | 5/17/2019 12:00:00 AM | |
| dc.date.issued | 2019 | |
| dc.identifier.issn | 1043-7398 | |
| dc.identifier.other | ep_141_04_040801 | |
| dc.identifier.uri | http://yetl.yabesh.ir/yetl1/handle/yetl/4259123 | |
| dc.description.abstract | The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented. | |
| dc.publisher | American Society of Mechanical Engineers (ASME) | |
| dc.title | Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging | |
| dc.type | Journal Paper | |
| dc.journal.volume | 141 | |
| dc.journal.issue | 4 | |
| dc.journal.title | Journal of Electronic Packaging | |
| dc.identifier.doi | 10.1115/1.4043341 | |
| dc.journal.fristpage | 40801 | |
| dc.journal.lastpage | 040801-27 | |
| dc.tree | Journal of Electronic Packaging:;2019:;volume( 141 ):;issue: 004 | |
| dc.contenttype | Fulltext | |
