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    An Experimental Investigation on the Fluid Distribution in a Two-Phase Cooled Rack Under Steady and Transient Information Technology Loads 

    Source: Journal of Electronic Packaging:;2020:;volume( 142 ):;issue: 004:;page 041002-1
    Author(s): Khalili, Sadegh; Rangarajan, Srikanth; Gektin, Vadim; Alissa, Husam; Sammakia, Bahgat
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: Increasing power densities in data centers due to the rise of artificial intelligence, high-performance computing, and machine learning compel engineers to develop new cooling strategies and designs for high-performance ...
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    Experimental Characterization of Two-Phase Cold Plates Intended for High-Density Data Center Servers Using a Dielectric Fluid 

    Source: Journal of Electronic Packaging:;2021:;volume( 143 ):;issue: 002:;page 020904-1
    Author(s): Ramakrishnan, Bharath; Hoang, Cong Hiep; Khalili, Sadegh; Hadad, Yaser; Rangarajan, Srikanth; Pattamatta, Arvind; Sammakia, Bahgat
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: High-performance computing (HPC) data centers demand cutting edge cooling techniques like direct contact liquid cooling (DCLC) for safe and secure operation of their high-power density servers. The two-phase flow boiling ...
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    Minimizing the Effects of On-Chip Hotspots Using Multi-Objective Optimization of Flow Distribution in Water-Cooled Parallel Microchannel Heatsinks 

    Source: Journal of Electronic Packaging:;2020:;volume( 143 ):;issue: 002:;page 021007-1
    Author(s): Hadad, Yaser; Radmard, Vahideh; Rangarajan, Srikanth; Farahikia, Mahdi; Refai-Ahmed, Gamal; Chiarot, Paul R.; Sammakia, Bahgat
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: The industry shift to multicore microprocessor architecture will likely cause higher temperature nonuniformity on chip surfaces, exacerbating the problem of chip reliability and lifespan. While advanced cooling technologies ...
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    Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits 

    Source: Journal of Electronic Packaging:;2020:;volume( 142 ):;issue: 004:;page 041109-1
    Author(s): Rangarajan, Srikanth; Hadad, Yaser; Choobineh, Leila; Sammakia, Bahgat
    Publisher: The American Society of Mechanical Engineers (ASME)
    Abstract: The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically ...
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    DSpace software copyright © 2002-2015  DuraSpace
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