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dc.contributor.authorSesek, Aleksander
dc.contributor.authorChambers, Olga
dc.contributor.authorTrontelj, Janez
dc.date.accessioned2019-09-18T09:04:01Z
dc.date.available2019-09-18T09:04:01Z
dc.date.copyright3/4/2019 12:00:00 AM
dc.date.issued2019
dc.identifier.issn1043-7398
dc.identifier.otherep_141_02_021005.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4258458
dc.description.abstractPower electronic components' reliability depends, to a great extent, on the quality of die-attach technology. The voids appearance in the die-attach regions is almost unavoidable during the manufacturing process. The aim of this paper is to demonstrate that image processing tools enable fast and accurate void segmentation, while reducing manual interaction for X-ray monitoring of imperfect power transistor die soldering. The most common void parameters such as void area, void distribution, and shape roundness were extracted and used for statistical analysis.
dc.publisherAmerican Society of Mechanical Engineers (ASME)
dc.titleStudy on the Die-Attach Voids Distribution With X-Ray and Image Processing Techniques
dc.typeJournal Paper
dc.journal.volume141
dc.journal.issue2
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.4042804
dc.journal.fristpage21005
dc.journal.lastpage021005-7
dc.treeJournal of Electronic Packaging:;2019:;volume( 141 ):;issue: 002
dc.contenttypeFulltext


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