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dc.contributor.authorNokhosteen, Arman
dc.contributor.authorSoltani, M.
dc.contributor.authorBarabadi, Banafsheh
dc.date.accessioned2019-03-17T10:10:21Z
dc.date.available2019-03-17T10:10:21Z
dc.date.copyright2/25/2019 12:00:00 AM
dc.date.issued2019
dc.identifier.issn1043-7398
dc.identifier.otherep_141_01_011002.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4255967
dc.description.abstractThe high current densities in today's microelectronic devices and microchips lead to hotspot formations and other adverse effects on their performance. Therefore, a computational tool is needed to not only analyze but also accurately predict spatial and temporal temperature distribution while minimizing the computational effort within the chip architecture. In this study, a proper orthogonal decomposition (POD)-Galerkin projection-based reduced order model (ROM) was developed for modeling transient heat transfer in three-dimensional (3D) microchip interconnects. comsol software was used for producing the required data for ROM and for verifying the results. The developed technique has the ability to provide accurate results for various boundary conditions on the chip and interconnects domain and is capable of providing accurate results for nonlinear conditions, where thermal conductivity is temperature dependent. It is demonstrated in this work that a limited number of observations are sufficient for mapping out the entire evolution of temperature field within the domain for transient boundary. Furthermore, the accuracy of the results obtained from the developed ROM and the stability of accuracy over time is investigated. Finally, it is shown that the developed technique provides a 60-fold reduction in simulation time compared to finite element techniques.
dc.publisherThe American Society of Mechanical Engineers (ASME)
dc.titleReduced Order Modeling of Transient Heat Transfer in Microchip Interconnects
dc.typeJournal Paper
dc.journal.volume141
dc.journal.issue1
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.4041666
dc.journal.fristpage11002
dc.journal.lastpage011002-9
dc.treeJournal of Electronic Packaging:;2019:;volume( 141 ):;issue: 001
dc.contenttypeFulltext


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