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dc.contributor.authorGeng, Phil
dc.date.accessioned2019-03-17T10:10:19Z
dc.date.available2019-03-17T10:10:19Z
dc.date.copyright2/25/2019 12:00:00 AM
dc.date.issued2019
dc.identifier.issn1043-7398
dc.identifier.otherep_141_01_010801.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl1/handle/yetl/4255965
dc.description.abstractFor more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.
dc.publisherThe American Society of Mechanical Engineers (ASME)
dc.titleStructural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack Retention
dc.typeJournal Paper
dc.journal.volume141
dc.journal.issue1
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.4042800
dc.journal.fristpage10801
dc.journal.lastpage010801-8
dc.treeJournal of Electronic Packaging:;2019:;volume( 141 ):;issue: 001
dc.contenttypeFulltext


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