Thermal Cycling Study of Quilt Packaging

Abstract

The continued progress of microelectronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chippackaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packagingآ® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawidebandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quiltâ€‌ of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical highstress regions previously identified by finiteelement modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 آ°C to 125 آ°C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focusedionbeam crosssectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.