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dc.contributor.authorLorenzini
dc.contributor.authorKandlikar, Satish G.
dc.date.accessioned2017-05-09T01:06:48Z
dc.date.available2017-05-09T01:06:48Z
dc.date.issued2014
dc.identifier.issn1528-9044
dc.identifier.otherep_136_02_021007.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl/handle/yetl/154465
dc.description.abstractThe surface temperature of integrated circuit (IC) chips cooled with a singlephase liquid flow increases along the flow direction following the increase in the liquid temperature. Increasing the heat transfer coefficient along the flow direction is an effective way to enhance the cooling performance while mitigating the temperature nonuniformity and high pressure drop concerns. This investigation evaluates numerically the cooling performance of different flow channel designs suitable in 3D IC applications with channel heights restricted to 100 خ¼m. Internal configurations featuring offset strip fins with variable fin density and variable spacing ribs were studied in an effort to minimize the temperature nonuniformity while maintaining a relatively low pressure drop. The performance of 13 different designs for the variablefindensity configuration and three different rib configurations have been evaluated and compared with two baseline cases, corresponding to a smooth flow channel and a flow channel with continuous fins. All of the analyzed internal configurations are contained within a flow channel of 100 خ¼m height and 910 خ¼m width. A coolant chip formed by nine flow channels for the dissipation of 200 W of a 3D IC with a surface area of 1 cm2 is the base for this investigation. The best performing configuration resulted in a temperature variation of less than 30 K with a pressure drop of 34 kPa as compared to a temperature variation of 38 K and a pressure drop of 144 kPa with continuous fins and 51 K and 21 kPa for a smooth flow channel.
dc.publisherThe American Society of Mechanical Engineers (ASME)
dc.titleVariable Fin Density Flow Channels for Effective Cooling and Mitigation of Temperature Nonuniformity in Three Dimensional Integrated Circuits
dc.typeJournal Paper
dc.journal.volume136
dc.journal.issue2
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.4027091
dc.journal.fristpage21007
dc.journal.lastpage21007
dc.identifier.eissn1043-7398
dc.treeJournal of Electronic Packaging:;2014:;volume( 136 ):;issue: 002
dc.contenttypeFulltext


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