| dc.contributor.author | Hsien-Cheng Tseng | |
| dc.date.accessioned | 2017-05-09T00:43:14Z | |
| dc.date.available | 2017-05-09T00:43:14Z | |
| dc.date.copyright | March, 2011 | |
| dc.date.issued | 2011 | |
| dc.identifier.issn | 1528-9044 | |
| dc.identifier.other | JEPAE4-26312#014501_1.pdf | |
| dc.identifier.uri | http://yetl.yabesh.ir/yetl/handle/yetl/145827 | |
| dc.description.abstract | Advanced collector-up (C-up) heterojunction bipolar transistors (HBTs) with the thermal-via configuration (TVC) have been analyzed using a genetic algorithm (GA). Novel packaging structures are presented and evaluated in detail. With careful optimization, the thermal performance can be maximized by improving the thermal resistance over 40%, and the conventional TVC can be further reduced by 35%. The proposed approach is demonstrated on the multifinger InGaP/GaAs C-up HBT, which is attractive as the active component in power amplifiers. A comparison of measured, finite-element-calculated, and GA-extracted results has been made. Consequently, it is shown that the remarkable thermal management can be achieved with a miniature heat-dissipation design, and the thermally stable InGaP/GaAs C-up HBT should be feasible for implementation in intelligent wireless communication systems. | |
| dc.publisher | The American Society of Mechanical Engineers (ASME) | |
| dc.title | Improved Packaging Design for Maximizing the Thermal Performance of Multifinger Collector-Up HBTs | |
| dc.type | Journal Paper | |
| dc.journal.volume | 133 | |
| dc.journal.issue | 1 | |
| dc.journal.title | Journal of Electronic Packaging | |
| dc.identifier.doi | 10.1115/1.4003515 | |
| dc.journal.fristpage | 14501 | |
| dc.identifier.eissn | 1043-7398 | |
| dc.keywords | Design | |
| dc.keywords | Optimization | |
| dc.keywords | Packaging | |
| dc.keywords | Thermal resistance | |
| dc.keywords | Gallium arsenide AND Transistors | |
| dc.tree | Journal of Electronic Packaging:;2011:;volume( 133 ):;issue: 001 | |
| dc.contenttype | Fulltext | |