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dc.contributor.authorBrian D. Roggeman
dc.contributor.authorVenkatesh Raghavan
dc.contributor.authorPeter Borgesen
dc.date.accessioned2017-05-09T00:43:09Z
dc.date.available2017-05-09T00:43:09Z
dc.date.copyrightSeptember, 2011
dc.date.issued2011
dc.identifier.issn1528-9044
dc.identifier.otherJEPAE4-26316#031007_1.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl/handle/yetl/145787
dc.description.abstractThe introduction of less compliant lead free solders together with weaker and more brittle laminate materials has led to major concerns with respect to the resistance of the latter to pad cratering. For purposes of laminate selection as well as for the quantification of acceptable handling and use conditions, there is a general interest in the testing for cratering at the joint level, rather than by testing entire assemblies. Joint level testing is cheaper, faster, and offers more quantitative results. Joint level testing also allows the elimination of confounding factors such as PCB and component stiffness. Developing test procedures and testing, it is important to distinguish between wear out under repeated loads and the failure due to a single overstress. Correlations between these two damage scenarios are largely fortuitous. Focusing on strength testing we have compared alternative methods and identified the most relevant approach. Occasions may arise where shear testing is the most appropriate, but most pad cratering scenarios are best represented by so-called Hot Bump Pull at an angle of about 30° to the pad normal. Replacing the solder balls by paste deposits or pulling in a direction normal to the pad may lead to a different ranking of materials and otherwise obscure systematic trends. We also recommend taking loading rate and temperature effects into account.
dc.publisherThe American Society of Mechanical Engineers (ASME)
dc.titleJoint Level Test Methods for Solder Pad Cratering Investigations
dc.typeJournal Paper
dc.journal.volume133
dc.journal.issue3
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.4004182
dc.journal.fristpage31007
dc.identifier.eissn1043-7398
dc.keywordsSolders
dc.keywordsLaminates
dc.keywordsStress
dc.keywordsShear (Mechanics)
dc.keywordsTesting
dc.keywordsFailure
dc.keywordsResins AND Temperature
dc.treeJournal of Electronic Packaging:;2011:;volume( 133 ):;issue: 003
dc.contenttypeFulltext


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