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dc.contributor.authorSaketh Mahalingam
dc.contributor.authorAnanth Prabhakumar
dc.contributor.authorSuresh K. Sitaraman
dc.contributor.authorSandeep Tonapi
dc.date.accessioned2017-05-09T00:27:32Z
dc.date.available2017-05-09T00:27:32Z
dc.date.copyrightDecember, 2008
dc.date.issued2008
dc.identifier.issn1528-9044
dc.identifier.otherJEPAE4-26289#041005_1.pdf
dc.identifier.urihttp://yetl.yabesh.ir/yetl/handle/yetl/137737
dc.description.abstractThe occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.
dc.publisherThe American Society of Mechanical Engineers (ASME)
dc.titleTheoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials
dc.typeJournal Paper
dc.journal.volume130
dc.journal.issue4
dc.journal.titleJournal of Electronic Packaging
dc.identifier.doi10.1115/1.3010378
dc.journal.fristpage41005
dc.identifier.eissn1043-7398
dc.keywordsFlow (Dynamics)
dc.keywordsDelamination
dc.keywordsFlip-chip assemblies
dc.keywordsSolders AND Fatigue
dc.treeJournal of Electronic Packaging:;2008:;volume( 130 ):;issue: 004
dc.contenttypeFulltext


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