An Exergy-Based Figure-of-Merit for Electronic Packages

Abstract

Chip power consumption and heat dissipation have become important design issues because of increased energy costs and thermal management limitations. As a global compute utility evolves, seamless connectivity from the chip to the data center will become increasingly important. The optimization of such an infrastructure will require performance metrics that can adequately capture the thermodynamic and compute behavior at multiple physical length scales. In this paper, an exergy-based figure-of-merit (FoM), defined as the ratio of computing performance (in MIPS) to the thermodynamic performance (in exergy loss), is proposed for the evaluation of computational performance. The paper presents the framework to apply this metric at the chip level. Formulations for the exergy loss in simple air-cooled heat sink packages are developed, and application of the proposed approach is illustrated through two examples. The first comparatively assesses the loss in performance resulting from different cooling solutions, while the second examines the impact of non-uniformity in junction power in terms of the FoM. Modeling results on a 16mm×24mm chip indicate that uniform power and temperature profiles lead to minimal package irreversibility (and therefore the best thermodynamic performance). As the nonuniformity of power is increased, the performance rapidly degrades, particularly at higher power levels. Additionally, the competing needs of minimization of junction temperature and minimization of cooling power were highlighted using the exergy-based approach. It was shown that for a given power dissipation and a specific cooling architecture (such as an air-cooled heat sink solution), an optimal thermal resistance value exists beyond which the costs of increased cooling may outweigh any potential benefits in performance. Thus, the proposed FoM provides insight into thermofluidic inefficiencies that would be difficult to gain from a traditional first-law analysis. At a minimum, the framework presented in this paper enables quantitative evaluation of package performance for different nonuniform power inputs and different choices of cooling parameters. At best, since the FoM is scalable, the proposed metric has the potential to enable a chip-to-data-center strategy for optimal resource allocation.