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contributor authorM. A. Butterbaugh
date accessioned2017-05-08T23:53:09Z
date available2017-05-08T23:53:09Z
date copyrightDecember, 1997
date issued1997
identifier issn1528-9044
identifier otherJEPAE4-26163#288_1.pdf
identifier urihttp://yetl.yabesh.ir/yetl/handle/yetl/118516
description abstractThe customary one-dimensional thermal resistance model used for single chip modules is not well suited for use with multichip modules. In this paper, it is proposed to model a multichip module (MCM) using a two matrix approach. An external matrix of influence coefficients is used in conjunction with cap temperatures measured above each chip site to determine individual chip powers within the MCM. These chip powers are then used with a matrix of internal influence coefficients to determine chip temperature rise relative to the cap temperature. The proposed matrices are determined using a “thermal test module” or “computational model” where chip power, chip temperature, and cap temperature can be explicitly measured. This dual matrix model is then available for use with production modules to determine chip powers and temperatures from a measurement of cap temperatures above each chip-site. The proposed model is demonstrated for a four chip MCM using data from numerical simulations. A sample of test runs using the model predicts the chip powers and temperatures to within 3.5 and 5.5 percent, respectively, of the values from the numerical model. Module physical properties are also parametrically varied to determine their effect on matrix elements. The matrix model is also proposed as a design tool to augment more numerically intensive methods of thermal analysis.
publisherThe American Society of Mechanical Engineers (ASME)
titleDevelopment of a Two Matrix Model for Thermal Analysis of a Multichip Module
typeJournal Paper
journal volume119
journal issue4
journal titleJournal of Electronic Packaging
identifier doi10.1115/1.2792251
journal fristpage288
journal lastpage293
identifier eissn1043-7398
keywordsThermal analysis
treeJournal of Electronic Packaging:;1997:;volume( 119 ):;issue: 004
contenttypeFulltext


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