<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:dc="http://purl.org/dc/elements/1.1/" version="2.0">
<channel>
<title>Journal of Electronic Packaging</title>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/19053</link>
<description/>
<pubDate>Sat, 11 Apr 2026 15:26:25 GMT</pubDate>
<dc:date>2026-04-11T15:26:25Z</dc:date>
<image>
<title>Journal of Electronic Packaging</title>
<url>http://localhost:80/yetl1/bitstream/id/184273/</url>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/19053</link>
</image>
<item>
<title>Optimization of the Reliability of Ball Grid Array Solder Joints Under Random Vibration Conditions Using an Improved Back Propagation Neural Network-Based Particle Swarm Algorithm</title>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/4310329</link>
<description>Optimization of the Reliability of Ball Grid Array Solder Joints Under Random Vibration Conditions Using an Improved Back Propagation Neural Network-Based Particle Swarm Algorithm
Zhu, Miao; Yang, Xuexia; Sun, Yanxi; Lin, Jinbao; Liu, Erqiang; Wang, Ze
</description>
<pubDate>Wed, 01 Jan 2025 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://yetl.yabesh.ir/yetl1/handle/yetl/4310329</guid>
<dc:date>2025-01-01T00:00:00Z</dc:date>
</item>
<item>
<title>Evaluation of Phase Transformation on Boron Decorated Sn-1.5Ag-0.7 Cu Joined Cu Pillar for Packaging Connection</title>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/4310324</link>
<description>Evaluation of Phase Transformation on Boron Decorated Sn-1.5Ag-0.7 Cu Joined Cu Pillar for Packaging Connection
Ho, Ching-Yuan; Lee, Haw-Teng
The microstructure transformation, mechanical properties, and fracture behavior of boron (B) decorated tin (Sn)-1.5%Ag-0.7%copper (Cu) (SAC157) solder joints with Cu pillars were analyzed. Three concentrations of B (0.015%, 0.020%, and 0.025%) were evenly mixed into the SAC157 solders. The addition of B refined the primary β-Sn phase and transformed the eutectic phase Ag3Sn from a plate-like structure to a dense stripe configuration. During high-temperature storage, coarse intermetallic compounds (IMCs) that extruded into the primary β-Sn in SAC157 solder were observed, and the growth of IMCs was inhibited by B-pinning boundary motion. Furthermore, the B additive simultaneously increased hardness and improved ductility by reducing grain size. In shear strength tests, the SAC157 solder exhibited a brittle fracture surface with a shorter displacement of 0.78 mm, compared to 1.2 mm of elongation in B-decorated SAC157 solders, which displayed ductile properties characterized by a dimpled fracture surface. In conclusion, B particles acted as heterogeneous nucleation sites, effectively refining the grain structure, inhibiting the growth of the eutectic phase, and simultaneously enhancing ductility without compromising hardness.
</description>
<pubDate>Wed, 01 Jan 2025 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://yetl.yabesh.ir/yetl1/handle/yetl/4310324</guid>
<dc:date>2025-01-01T00:00:00Z</dc:date>
</item>
<item>
<title>Computational Framework for Computational Fluid Dynamics Analysis of Loop Thermosiphon Based Embedded Cooling Systems</title>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/4310317</link>
<description>Computational Framework for Computational Fluid Dynamics Analysis of Loop Thermosiphon Based Embedded Cooling Systems
Kiper, Caner Ekin; Gallego-Marcos, Ignacio; Van Wyk, Stevin; Akkus, Yigit
Loop thermosiphons (LTSs) are highly effective two-phase heat spreaders, enabling significant heat transport through passive liquid–vapor phase-change, particularly beneficial in electronics cooling. However, prior studies on LTS simulations often lack sufficient clarity regarding critical modeling assumptions—particularly the selection of mass relaxation coefficients in the Lee phase-change model—and omit detailed analysis of the interplay between key numerical and physical parameters. These gaps present challenges for thermal engineers and researchers in developing stable, reliable volume of fluid (VOF) based computational fluid dynamics (CFD) simulations. In this study, we address these issues by proposing a computational framework that systematically examines the impact of parameters such as numerical time-step, flow regime, and mass relaxation coefficient ratios on stability and convergence. By monitoring and controlling mass variation, we demonstrate stable simulations with time-steps ranging from 1 × 10−4 to 5 × 10−4 s, using both turbulent and laminar flow assumptions and density-ratio-based mass relaxation coefficients. Our findings also highlight that an explicit discretization scheme combined with Geo-Reconstruct for volume fraction calculations significantly enhances stability. This framework thus provides a clear, systematic approach to LTS VOF modeling, offering a practical “recipe” for ensuring numerical robustness and guiding thermal engineers in navigating complex simulation settings.
</description>
<pubDate>Wed, 01 Jan 2025 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://yetl.yabesh.ir/yetl1/handle/yetl/4310317</guid>
<dc:date>2025-01-01T00:00:00Z</dc:date>
</item>
<item>
<title>Flow Characterization of Capillary Underfill in Multi-Chip Heterogenous Integration Using Computational Fluid Dynamics</title>
<link>http://yetl.yabesh.ir/yetl1/handle/yetl/4310311</link>
<description>Flow Characterization of Capillary Underfill in Multi-Chip Heterogenous Integration Using Computational Fluid Dynamics
Azman, Muhammad Aqil; Abdullah, Mohd Zulkifly; Loh, Wei Keat; Ooi, Chun Keang
Underfill encapsulation is crucial in assembling flip-chip products, such as ball grid array packages, enhancing the reliability and performance of electronic packages by filling voids between integrated circuit chips and substrates. Despite advancements, challenges remain in understanding underfill flow dynamics in multichip heterogeneous systems. This study explores capillary underfill encapsulation in quad-chip configurations, integrating experimental observations with computational fluid dynamics (CFD) simulations to analyze underfill flow dynamics and their impact on package reliability. The CFD model shows high accuracy, with validation errors as low as 5.31% at a normalized time (tnz) of 0.02, 6.83% at 0.1, and 6.05% at 0.2. Among dispensing patterns, the Double-I pattern is most effective, minimizing void formation with percentages as low as 0.02%, compared to up to 1.96% and 2.39% for L and U patterns, respectively. The study also identifies an optimal dispensing length of 50% of the total chip length, reducing void percentages to 0.04%, compared to 9.32% and 12.84% at 100% and 30% lengths, respectively. These findings are pivotal for optimizing underfill processes, enhancing electronic package reliability and performance. The insights gained are crucial for advancing the design and manufacturing of state-of-the-art electronic devices, particularly in complex, heterogeneous integrations. This work provides a robust framework for improving the efficiency and reliability of electronic packaging solutions, paving the way for more durable and high-performance electronic devices.
</description>
<pubDate>Wed, 01 Jan 2025 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://yetl.yabesh.ir/yetl1/handle/yetl/4310311</guid>
<dc:date>2025-01-01T00:00:00Z</dc:date>
</item>
</channel>
</rss>
